mbist 4 dalawahan port ram

H

HolySaint

Guest
aking ram ay binuo sa pamamagitan ng memery tagatala

kapag ako gen ang bist ctrl, i SIM ito

ngunit ang fail_h signal ay mataas
Dont ako kung bakit ang output ay 'X'

tingnan ang larawan<img src="http://images.elektroda.net/22_1228735865_thumb.jpg" border="0" alt="mbist 4 dual port ram" title="mbist 4 dalawahan port ram"/>

<img src="http://images.elektroda.net/32_1228798488_thumb.jpg" border="0" alt="mbist 4 dual port ram" title="mbist 4 dalawahan port ram"/>Huling-edit sa pamamagitan ng HolySaint sa 09 Dec 2008 6:55; edit 1 oras sa kabuuang

 
Hi holysaint

May maaaring maraming posibilidad.
Siguro ang memorya ng modelo na ito ay hindi tama.
Siguro ang kapanggapan mga opsyon ay hindi tama.

Ako ay pumunta sa mismong lugar kung saan i-check ang fail_h pumunta mataas.Kung ang memorya ng output ay X, may maaaring tiyempo paglabag.

 
Hi holysaint

Ito mukhang talagang weird na test_QA pumunta sa X bigla kapag nagbabasa ang address 0xB70.Naisip mo na-check na ang tiyak na halaga ay isinulat int o 0xB70 bago ito?

 
paumanhin
ako magbibigay ng maling pic

tumingin na muli

ang unang bigyan ng data
ang sceond basahin ang dataAdded matapos 7 minuto:ang ram ay sa ibaba:

Code:

/ /

/ / Kompidensiyal at pag-aari na SOFTWARE NG braso Pisikal IP, Inc

/ /

/ / Copyright (c) 1993-2008 braso Pisikal IP, Inc All Rights Reserved.

/ /

/ / Gumamit ng software na ito ay napapailalim sa mga kasunduan at kondisyon ng

/ / Naaangkop sa lisensiya kasunduan sa braso Pisikal na IP, Inc Sa karagdagan,

/ / Software na ito ay protektado ng patente, batas sa karapatang-kopya at pang-internasyonal na

/ / Treaties.

/ /

/ / Ang copyright (s) sa Software na ito ay hindi nagpapahiwatig ng aktwal na o

/ / Inilaan publikasyon ng Software.

/ /

/ / Name: Mataas na Speed / Densidad dalawahan-Port SRAM Generator

/ / SMIC 0.18um Logic018 Proseso

/ / Bersyon: 2005Q3V1

/ / Comment:

/ / Configuration:-instname "test_ram"-salita 576-bits 32 dalas-67-ring_width 5-mux 4-drive 12-write_mask off-wp_size 8-top_layer met5-power_type rings-horiz met4-vert met4-cust_comment "" -- left_bus_delim "["-right_bus_delim "]"-pwr_gnd_rename "VDD: VDD, GND: VSS"-prefix ""-pin_space 0.0-name_case itaas na-check_instname sa diodes-sa-inside_ring_type GND-dpccm sa asvm-off

/ /

/ / Verilog modelo para sa mga kasabay dalawahan-Port Ram

/ /

/ / Pagkakataon Pangalan: test_ram

/ / Words: 576

/ / Word Lawak: 32

/ / Tubo: Hindi

/ /

/ / Creation Date: 2008-08-12 07:22:46 Z

/ / Version: 2005Q3V1

/ /

/ / Verified Sa: indayog Verilog-XL

/ /

/ / Pagmomolde pagpapalagay: Ang modelo ay sumusuporta sa buong gate antas kunwa

/ / Kabilang ang tamang x-handle at i-check tiyempo na pag-uugali. Unit

/ / Pagkaantala tiyempo ay kasama sa mga modelo.
Balik-annotation ng SDF

/ / (V2.1) ay suportado. SDF ay maaaring nilikha utilyzing ang delay

/ / Pagkalkula views na ibinigay sa mga ito dyeneretor at suportado

/ / Pagkaantala calculators. Lahat ng mga bus ay modeled [MSB: LSB]. Lahat

/ / Port ay may mga palaman sa Verilog primitives.

/ /

/ / Pagmomolde Limitasyon: Ang output hold function na ito ay tinanggal na

/ / Mula sa ganap na modelo. Karamihan Verilog simulators ay

/ / Hindi kaya ng pag-iiskedyul ng higit sa 1 kaganapan sa pagsikat

/ / Gilid ng orasan. Samakatuwid, ito ay imposible na modelo

/ / Ang output hold (sa x) action ng maayos. Ito ay kinakailangan

/ / Na tumakbo static path tiyempo tools gamit Artisan ibinibigay

/ / Tiyempo modelo na siguraduhin na ang output hold na panahon ay

/ / Ng sapat na sapat na upang hindi lumalabag sa hold oras constraints

/ / Sa ibaba ng agos ng flip-flops.

/ /

/ / Kilalang Bugs: Wala.

/ /

/ / Kilalang Work Arounds: N / A

/ /

`timescale 1 ns / 1 PS

`celldefine

module test_ram (

QA,

CLKA,

CENA,

WENA,

Aa,

DA,

OENA,

QB,

CLKB,

CENB,

WENB,

AB,

DB,

OENB

);

parameter Bits = 32;

parameter word_depth = 576;

parameter addr_width = 10;

parameter wordx = ((Bits 1'bx));

parameter addrx = (addr_width (1'bx));output [31:0] QA;

input CLKA;

input CENA;

input WENA;

input [9:0] Aa;

input [31:0] DA;

input OENA;

output [31:0] QB;

input CLKB;

input CENB;

input WENB;

input [9:0] AB;

input [31:0] DB;

input OENB;reg [Bits-1: 0] mem [word_depth-1: 0];

reg NOT_CONTA;

reg NOT_CONTB;reg NOT_CENA;

reg NOT_WENA;reg NOT_AA0;

reg NOT_AA1;

reg NOT_AA2;

reg NOT_AA3;

reg NOT_AA4;

reg NOT_AA5;

reg NOT_AA6;

reg NOT_AA7;

reg NOT_AA8;

reg NOT_AA9;

reg [addr_width-1: 0] NOT_AA;

reg NOT_DA0;

reg NOT_DA1;

reg NOT_DA2;

reg NOT_DA3;

reg NOT_DA4;

reg NOT_DA5;

reg NOT_DA6;

reg NOT_DA7;

reg NOT_DA8;

reg NOT_DA9;

reg NOT_DA10;

reg NOT_DA11;

reg NOT_DA12;

reg NOT_DA13;

reg NOT_DA14;

reg NOT_DA15;

reg NOT_DA16;

reg NOT_DA17;

reg NOT_DA18;

reg NOT_DA19;

reg NOT_DA20;

reg NOT_DA21;

reg NOT_DA22;

reg NOT_DA23;

reg NOT_DA24;

reg NOT_DA25;

reg NOT_DA26;

reg NOT_DA27;

reg NOT_DA28;

reg NOT_DA29;

reg NOT_DA30;

reg NOT_DA31;

reg [Bits-1: 0] NOT_DA;

reg NOT_CLKA_PER;

reg NOT_CLKA_MINH;

reg NOT_CLKA_MINL;

reg NOT_CENB;

reg NOT_WENB;reg NOT_AB0;

reg NOT_AB1;

reg NOT_AB2;

reg NOT_AB3;

reg NOT_AB4;

reg NOT_AB5;

reg NOT_AB6;

reg NOT_AB7;

reg NOT_AB8;

reg NOT_AB9;

reg [addr_width-1: 0] NOT_AB;

reg NOT_DB0;

reg NOT_DB1;

reg NOT_DB2;

reg NOT_DB3;

reg NOT_DB4;

reg NOT_DB5;

reg NOT_DB6;

reg NOT_DB7;

reg NOT_DB8;

reg NOT_DB9;

reg NOT_DB10;

reg NOT_DB11;

reg NOT_DB12;

reg NOT_DB13;

reg NOT_DB14;

reg NOT_DB15;

reg NOT_DB16;

reg NOT_DB17;

reg NOT_DB18;

reg NOT_DB19;

reg NOT_DB20;

reg NOT_DB21;

reg NOT_DB22;

reg NOT_DB23;

reg NOT_DB24;

reg NOT_DB25;

reg NOT_DB26;

reg NOT_DB27;

reg NOT_DB28;

reg NOT_DB29;

reg NOT_DB30;

reg NOT_DB31;

reg [Bits-1: 0] NOT_DB;

reg NOT_CLKB_PER;

reg NOT_CLKB_MINH;

reg NOT_CLKB_MINL;reg LAST_NOT_CENA;

reg LAST_NOT_WENA;

reg [addr_width-1: 0] LAST_NOT_AA;

reg [Bits-1: 0] LAST_NOT_DA;

reg LAST_NOT_CLKA_PER;

reg LAST_NOT_CLKA_MINH;

reg LAST_NOT_CLKA_MINL;

reg LAST_NOT_CENB;

reg LAST_NOT_WENB;

reg [addr_width-1: 0] LAST_NOT_AB;

reg [Bits-1: 0] LAST_NOT_DB;

reg LAST_NOT_CLKB_PER;

reg LAST_NOT_CLKB_MINH;

reg LAST_NOT_CLKB_MINL;reg LAST_NOT_CONTA;

reg LAST_NOT_CONTB;

kawad contA_flag;

kawad contB_flag;

kawad cont_flag;kawad [Bits-1: 0] _QA;

kawad _OENAi;

telegrama [addr_width-1: 0] _AA;

kawad _CLKA;

kawad _CENA;

kawad _OENA;

kawad _WENA;kawad [Bits-1: 0] _DA;

kawad re_flagA;

kawad re_data_flagA;kawad [Bits-1: 0] _QB;

kawad _OENBi;

telegrama [addr_width-1: 0] _AB;

kawad _CLKB;

kawad _CENB;

kawad _OENB;

kawad _WENB;kawad [Bits-1: 0] _DB;

kawad re_flagB;

kawad re_data_flagB;reg LATCHED_CENA;

reg LATCHED_WENA;

reg [addr_width-1: 0] LATCHED_AA;

reg [Bits-1: 0] LATCHED_DA;

reg LATCHED_CENB;

reg LATCHED_WENB;

reg [addr_width-1: 0] LATCHED_AB;

reg [Bits-1: 0] LATCHED_DB;reg CENAi;

reg WENAi;

reg [addr_width-1: 0] AAi;

reg [Bits-1: 0] Dai;

reg [Bits-1: 0] QAi;

reg [Bits-1: 0] LAST_QAi;

reg CENBi;

reg WENBi;

reg [addr_width-1: 0] ABi;

reg [Bits-1: 0] DBi;

reg [Bits-1: 0] QBi;

reg [Bits-1: 0] LAST_QBi;
reg LAST_CLKA;

reg LAST_CLKB;
reg valid_cycleA;

reg valid_cycleB;gawain update_Anotifier_buses;

simulan

NOT_AA = (

NOT_AA9,

NOT_AA8,

NOT_AA7,

NOT_AA6,

NOT_AA5,

NOT_AA4,

NOT_AA3,

NOT_AA2,

NOT_AA1,

NOT_AA0);

NOT_DA = (

NOT_DA31,

NOT_DA30,

NOT_DA29,

NOT_DA28,

NOT_DA27,

NOT_DA26,

NOT_DA25,

NOT_DA24,

NOT_DA23,

NOT_DA22,

NOT_DA21,

NOT_DA20,

NOT_DA19,

NOT_DA18,

NOT_DA17,

NOT_DA16,

NOT_DA15,

NOT_DA14,

NOT_DA13,

NOT_DA12,

NOT_DA11,

NOT_DA10,

NOT_DA9,

NOT_DA8,

NOT_DA7,

NOT_DA6,

NOT_DA5,

NOT_DA4,

NOT_DA3,

NOT_DA2,

NOT_DA1,

NOT_DA0);

wakasan

endtask

gawain update_Bnotifier_buses;

simulan

NOT_AB = (

NOT_AB9,

NOT_AB8,

NOT_AB7,

NOT_AB6,

NOT_AB5,

NOT_AB4,

NOT_AB3,

NOT_AB2,

NOT_AB1,

NOT_AB0);

NOT_DB = (

NOT_DB31,

NOT_DB30,

NOT_DB29,

NOT_DB28,

NOT_DB27,

NOT_DB26,

NOT_DB25,

NOT_DB24,

NOT_DB23,

NOT_DB22,

NOT_DB21,

NOT_DB20,

NOT_DB19,

NOT_DB18,

NOT_DB17,

NOT_DB16,

NOT_DB15,

NOT_DB14,

NOT_DB13,

NOT_DB12,

NOT_DB11,

NOT_DB10,

NOT_DB9,

NOT_DB8,

NOT_DB7,

NOT_DB6,

NOT_DB5,

NOT_DB4,

NOT_DB3,

NOT_DB2,

NOT_DB1,

NOT_DB0);

wakasan

endtaskgawain mem_cycleA;

simulan

valid_cycleA = 1'bx;

casez ((WENAi, CENAi))2'b10: magsimula

valid_cycleA = 1;

read_memA (1,0);

wakasan

2'b00: magsimula

valid_cycleA = 0;

write_mem (AAi, Dai);

read_memA (0,0);

wakasan

2'b? 1:;

2'b1x: magsimula

valid_cycleA = 1;

read_memA (0,1);

wakasan

2'bx0: magsimula

valid_cycleA = 0;

write_mem_x (AAi);

read_memA (0,1);

wakasan

2'b0x,

2'bxx: magsimula

valid_cycleA = 0;

write_mem_x (AAi);

read_memA (0,1);

wakasan

endcase

wakasan

endtask

gawain mem_cycleB;

simulan

valid_cycleB = 1'bx;

casez ((WENBi, CENBi))2'b10: magsimula

valid_cycleB = 1;

read_memB (1,0);

wakasan

2'b00: magsimula

valid_cycleB = 0;

write_mem (ABi, DBi);

read_memB (0,0);

wakasan

2'b? 1:;

2'b1x: magsimula

valid_cycleB = 1;

read_memB (0,1);

wakasan

2'bx0: magsimula

valid_cycleB = 0;

write_mem_x (ABi);

read_memB (0,1);

wakasan

2'b0x,

2'bxx: magsimula

valid_cycleB = 0;

write_mem_x (ABi);

read_memB (0,1);

wakasan

endcase

wakasan

endtaskgawain contentionA;

simulan

casez ((valid_cycleB, WENAi))

2'bx?:;

2'b00,

2'b0x: magsimula

write_mem_x (AAi);

wakasan

2'b10,

2'b1x: magsimula

read_memB (0,1);

wakasan

2'b01: magsimula

read_memA (0,1);

wakasan

2'b11:;

endcase

wakasan

endtaskgawain contentionB;

simulan

casez ((valid_cycleA, WENBi))

2'bx?:;

2'b00,

2'b0x: magsimula

write_mem_x (ABi);

wakasan

2'b10,

2'b1x: magsimula

read_memA (0,1);

wakasan

2'b01: magsimula

read_memB (0,1);

wakasan

2'b11:;

endcase

wakasan

endtaskgawain update_Alast_notifiers;

simulan

LAST_NOT_AA = NOT_AA;

LAST_NOT_DA = NOT_DA;

LAST_NOT_WENA = NOT_WENA;

LAST_NOT_CENA = NOT_CENA;

LAST_NOT_CLKA_PER = NOT_CLKA_PER;

LAST_NOT_CLKA_MINH = NOT_CLKA_MINH;

LAST_NOT_CLKA_MINL = NOT_CLKA_MINL;

LAST_NOT_CONTA = NOT_CONTA;

wakasan

endtask

gawain update_Blast_notifiers;

simulan

LAST_NOT_AB = NOT_AB;

LAST_NOT_DB = NOT_DB;

LAST_NOT_WENB = NOT_WENB;

LAST_NOT_CENB = NOT_CENB;

LAST_NOT_CLKB_PER = NOT_CLKB_PER;

LAST_NOT_CLKB_MINH = NOT_CLKB_MINH;

LAST_NOT_CLKB_MINL = NOT_CLKB_MINL;

LAST_NOT_CONTB = NOT_CONTB;

wakasan

endtaskgawain latch_Ainputs;

simulan

LATCHED_AA = _AA;

LATCHED_DA = _DA;

LATCHED_WENA = _WENA;

LATCHED_CENA = _CENA;

LAST_QAi = QAi;

wakasan

endtask

gawain latch_Binputs;

simulan

LATCHED_AB = _AB;

LATCHED_DB = _DB;

LATCHED_WENB = _WENB;

LATCHED_CENB = _CENB;

LAST_QBi = QBi;

wakasan

endtaskgawain update_Alogic;

simulan

CENAi = LATCHED_CENA;

WENAi = LATCHED_WENA;

AAi = LATCHED_AA;

Dai = LATCHED_DA;

wakasan

endtask

gawain update_Blogic;

simulan

CENBi = LATCHED_CENB;

WENBi = LATCHED_WENB;

ABi = LATCHED_AB;

DBi = LATCHED_DB;

wakasan

endtask
gawain x_Ainputs;

integer n;

simulan

para sa (n = 0; n <addr_width; n = n 1)

simulan

LATCHED_AA [n] = (NOT_AA [n]! == LAST_NOT_AA [n])?
1'bx: LATCHED_AA [n];

wakasan

para sa (n = 0; n <Bits; n = n 1)

simulan

LATCHED_DA [n] = (NOT_DA [n]! == LAST_NOT_DA [n])?
1'bx: LATCHED_DA [n];

wakasan

LATCHED_WENA = (NOT_WENA! == LAST_NOT_WENA)?
1'bx: LATCHED_WENA;LATCHED_CENA = (NOT_CENA! == LAST_NOT_CENA)?
1'bx: LATCHED_CENA;

wakasan

endtask

gawain x_Binputs;

integer n;

simulan

para sa (n = 0; n <addr_width; n = n 1)

simulan

LATCHED_AB [n] = (NOT_AB [n]! == LAST_NOT_AB [n])?
1'bx: LATCHED_AB [n];

wakasan

para sa (n = 0; n <Bits; n = n 1)

simulan

LATCHED_DB [n] = (NOT_DB [n]! == LAST_NOT_DB [n])?
1'bx: LATCHED_DB [n];

wakasan

LATCHED_WENB = (NOT_WENB! == LAST_NOT_WENB)?
1'bx: LATCHED_WENB;LATCHED_CENB = (NOT_CENB! == LAST_NOT_CENB)?
1'bx: LATCHED_CENB;

wakasan

endtaskgawain read_memA;

input r_wb;

input xflag;

simulan

kung (r_wb)

simulan

kung (valid_address (AAi))

simulan

QAi = mem [AAi];

wakasan

kung hindi

simulan

x_mem;

QAi = wordx;

wakasan

wakasan

kung hindi

simulan

kung (xflag)

simulan

QAi = wordx;

wakasan

kung hindi

simulan

QAi = Dai;

wakasan

wakasan

wakasan

endtask

gawain read_memB;

input r_wb;

input xflag;

simulan

kung (r_wb)

simulan

kung (valid_address (ABi))

simulan

QBi = mem [ABi];

wakasan

kung hindi

simulan

x_mem;

QBi = wordx;

wakasan

wakasan

kung hindi

simulan

kung (xflag)

simulan

QBi = wordx;

wakasan

kung hindi

simulan

QBi = DBi;

wakasan

wakasan

wakasan

endtaskgawain write_mem;

input [addr_width-1: 0] isang;

input [Bits-1: 0] d;simulan

casez ((valid_address (a)))

1'b0:

x_mem;

1'b1: mem [isang] = d;

endcase

wakasan

endtaskgawain write_mem_x;

input [addr_width-1: 0] isang;

simulan

casez ((valid_address (a)))

1'b0:

x_mem;

1'b1: mem [isang] = wordx;

endcase

wakasan

endtaskgawain x_mem;

integer n;

simulan

para sa (n = 0; n <word_depth; n = n 1)

mem [n] = wordx;

wakasan

endtaskgawain process_violationsA;

simulan

kung ((NOT_CLKA_PER! == LAST_NOT_CLKA_PER) | |

(NOT_CLKA_MINH! == LAST_NOT_CLKA_MINH) | |

(NOT_CLKA_MINL! == LAST_NOT_CLKA_MINL))

simulan

kung (CENAi! == 1'b1)

simulan

x_mem;

read_memA (0,1);

wakasan

wakasan

kung hindi

simulan

update_Anotifier_buses;

x_Ainputs;

update_Alogic;

kung (NOT_CONTA! == LAST_NOT_CONTA)

simulan

contentionA;

wakasan

kung hindi

simulan

mem_cycleA;

wakasan

wakasan

update_Alast_notifiers;

wakasan

endtaskgawain process_violationsB;

simulan

kung ((NOT_CLKB_PER! == LAST_NOT_CLKB_PER) | |

(NOT_CLKB_MINH! == LAST_NOT_CLKB_MINH) | |

(NOT_CLKB_MINL! == LAST_NOT_CLKB_MINL))

simulan

kung (CENBi! == 1'b1)

simulan

x_mem;

read_memB (0,1);

wakasan

wakasan

kung hindi

simulan

update_Bnotifier_buses;

x_Binputs;

update_Blogic;

kung (NOT_CONTB! == LAST_NOT_CONTB)

simulan

contentionB;

wakasan

kung hindi

simulan

mem_cycleB;

wakasan

wakasan

update_Blast_notifiers;

wakasan

endtaskfunction valid_address;

input [addr_width-1: 0] isang;

simulan

valid_address = (^ (a)! == 1'bx);

wakasan

endfunctionbufif0 (QA [0], _QA [0], _OENAi);

bufif0 (QA [1], _QA [1], _OENAi);

bufif0 (QA [2], _QA [2], _OENAi);

bufif0 (QA [3], _QA [3], _OENAi);

bufif0 (QA [4], _QA [4], _OENAi);

bufif0 (QA [5], _QA [5], _OENAi);

bufif0 (QA [6], _QA [6], _OENAi);

bufif0 (QA [7], _QA [7], _OENAi);

bufif0 (QA [8], _QA [8], _OENAi);

bufif0 (QA [9], _QA [9], _OENAi);

bufif0 (QA [10], _QA [10], _OENAi);

bufif0 (QA [11], _QA [11], _OENAi);

bufif0 (QA [12], _QA [12], _OENAi);

bufif0 (QA [13], _QA [13], _OENAi);

bufif0 (QA [14], _QA [14], _OENAi);

bufif0 (QA [15], _QA [15], _OENAi);

bufif0 (QA [16], _QA [16], _OENAi);

bufif0 (QA [17], _QA [17], _OENAi);

bufif0 (QA [18], _QA [18], _OENAi);

bufif0 (QA [19], _QA [19], _OENAi);

bufif0 (QA [20], _QA [20], _OENAi);

bufif0 (QA [21], _QA [21], _OENAi);

bufif0 (QA [22], _QA [22], _OENAi);

bufif0 (QA [23], _QA [23], _OENAi);

bufif0 (QA [24], _QA [24], _OENAi);

bufif0 (QA [25], _QA [25], _OENAi);

bufif0 (QA [26], _QA [26], _OENAi);

bufif0 (QA [27], _QA [27], _OENAi);

bufif0 (QA [28], _QA [28], _OENAi);

bufif0 (QA [29], _QA [29], _OENAi);

bufif0 (QA [30], _QA [30], _OENAi);

bufif0 (QA [31], _QA [31], _OENAi);

buf (_DA [0], DA [0]);

buf (_DA [1], DA [1]);

buf (_DA [2], DA [2]);

buf (_DA [3], DA [3]);

buf (_DA [4], DA [4]);

buf (_DA [5], DA [5]);

buf (_DA [6], DA [6]);

buf (_DA [7], DA [7]);

buf (_DA [8], DA [8]);

buf (_DA [9], DA [9]);

buf (_DA [10], DA [10]);

buf (_DA [11], DA [11]);

buf (_DA [12], DA [12]);

buf (_DA [13], DA [13]);

buf (_DA [14], DA [14]);

buf (_DA [15], DA [15]);

buf (_DA [16], DA [16]);

buf (_DA [17], DA [17]);

buf (_DA [18], DA [18]);

buf (_DA [19], DA [19]);

buf (_DA [20], DA [20]);

buf (_DA [21], DA [21]);

buf (_DA [22], DA [22]);

buf (_DA [23], DA [23]);

buf (_DA [24], DA [24]);

buf (_DA [25], DA [25]);

buf (_DA [26], DA [26]);

buf (_DA [27], DA [27]);

buf (_DA [28], DA [28]);

buf (_DA [29], DA [29]);

buf (_DA [30], DA [30]);

buf (_DA [31], DA [31]);

buf (_AA [0], Aa [0]);

buf (_AA [1], Aa [1]);

buf (_AA [2], Aa [2]);

buf (_AA [3], Aa [3]);

buf (_AA [4], Aa [4]);

buf (_AA [5], Aa [5]);

buf (_AA [6], Aa [6]);

buf (_AA [7], Aa [7]);

buf (_AA [8], Aa [8]);

buf (_AA [9], Aa [9]);

buf (_CLKA, CLKA);

buf (_WENA, WENA);

buf (_OENA, OENA);

buf (_CENA, CENA);

bufif0 (QB [0], _QB [0], _OENBi);

bufif0 (QB [1], _QB [1], _OENBi);

bufif0 (QB [2], _QB [2], _OENBi);

bufif0 (QB [3], _QB [3], _OENBi);

bufif0 (QB [4], _QB [4], _OENBi);

bufif0 (QB [5], _QB [5], _OENBi);

bufif0 (QB [6], _QB [6], _OENBi);

bufif0 (QB [7], _QB [7], _OENBi);

bufif0 (QB [8], _QB [8], _OENBi);

bufif0 (QB [9], _QB [9], _OENBi);

bufif0 (QB [10], _QB [10], _OENBi);

bufif0 (QB [11], _QB [11], _OENBi);

bufif0 (QB [12], _QB [12], _OENBi);

bufif0 (QB [13], _QB [13], _OENBi);

bufif0 (QB [14], _QB [14], _OENBi);

bufif0 (QB [15], _QB [15], _OENBi);

bufif0 (QB [16], _QB [16], _OENBi);

bufif0 (QB [17], _QB [17], _OENBi);

bufif0 (QB [18], _QB [18], _OENBi);

bufif0 (QB [19], _QB [19], _OENBi);

bufif0 (QB [20], _QB [20], _OENBi);

bufif0 (QB [21], _QB [21], _OENBi);

bufif0 (QB [22], _QB [22], _OENBi);

bufif0 (QB [23], _QB [23], _OENBi);

bufif0 (QB [24], _QB [24], _OENBi);

bufif0 (QB [25], _QB [25], _OENBi);

bufif0 (QB [26], _QB [26], _OENBi);

bufif0 (QB [27], _QB [27], _OENBi);

bufif0 (QB [28], _QB [28], _OENBi);

bufif0 (QB [29], _QB [29], _OENBi);

bufif0 (QB [30], _QB [30], _OENBi);

bufif0 (QB [31], _QB [31], _OENBi);

buf (_DB [0], DB [0]);

buf (_DB [1], DB [1]);

buf (_DB [2], DB [2]);

buf (_DB [3], DB [3]);

buf (_DB [4], DB [4]);

buf (_DB [5], DB [5]);

buf (_DB [6], DB [6]);

buf (_DB [7], DB [7]);

buf (_DB [8], DB [8]);

buf (_DB [9], DB [9]);

buf (_DB [10], DB [10]);

buf (_DB [11], DB [11]);

buf (_DB [12], DB [12]);

buf (_DB [13], DB [13]);

buf (_DB [14], DB [14]);

buf (_DB [15], DB [15]);

buf (_DB [16], DB [16]);

buf (_DB [17], DB [17]);

buf (_DB [18], DB [18]);

buf (_DB [19], DB [19]);

buf (_DB [20], DB [20]);

buf (_DB [21], DB [21]);

buf (_DB [22], DB [22]);

buf (_DB [23], DB [23]);

buf (_DB [24], DB [24]);

buf (_DB [25], DB [25]);

buf (_DB [26], DB [26]);

buf (_DB [27], DB [27]);

buf (_DB [28], DB [28]);

buf (_DB [29], DB [29]);

buf (_DB [30], DB [30]);

buf (_DB [31], DB [31]);

buf (_AB [0], AB [0]);

buf (_AB [1], AB [1]);

buf (_AB [2], AB [2]);

buf (_AB [3], AB [3]);

buf (_AB [4], AB [4]);

buf (_AB [5], AB [5]);

buf (_AB [6], AB [6]);

buf (_AB [7], AB [7]);

buf (_AB [8], AB [8]);

buf (_AB [9], AB [9]);

buf (_CLKB, CLKB);

buf (_WENB, WENB);

buf (_OENB, OENB);

buf (_CENB, CENB);magtalaga ng _OENAi = _OENA;

magtalaga ng _QA = QAi;

magtalaga ng re_flagA =! (_CENA);

magtalaga ng re_data_flagA =! (_CENA | | _WENA);

magtalaga ng _OENBi = _OENB;

magtalaga ng _QB = QBi;

magtalaga ng re_flagB =! (_CENB);

magtalaga ng re_data_flagB =! (_CENB | | _WENB);magtalaga ng contA_flag =

(_AA === ABi) & &

! ((_WENA === 1'b1) & & (WENBi === 1'b1)) & &

(_CENA! == 1'b1) & &

(CENBi! == 1'b1);magtalaga ng contB_flag =

(_AB === AAi) & &

! ((_WENB === 1'b1) & & (WENAi === 1'b1)) & &

(_CENB! == 1'b1) & &

(CENAi! == 1'b1);magtalaga ng cont_flag =

(_AB === _AA) & &

! ((_WENB === 1'b1) & & (_WENA === 1'b1)) & &

(_CENB! == 1'b1) & &

(_CENA! == 1'b1);laging @ (

NOT_AA0 o

NOT_AA1 o

NOT_AA2 o

NOT_AA3 o

NOT_AA4 o

NOT_AA5 o

NOT_AA6 o

NOT_AA7 o

NOT_AA8 o

NOT_AA9 o

NOT_DA0 o

NOT_DA1 o

NOT_DA2 o

NOT_DA3 o

NOT_DA4 o

NOT_DA5 o

NOT_DA6 o

NOT_DA7 o

NOT_DA8 o

NOT_DA9 o

NOT_DA10 o

NOT_DA11 o

NOT_DA12 o

NOT_DA13 o

NOT_DA14 o

NOT_DA15 o

NOT_DA16 o

NOT_DA17 o

NOT_DA18 o

NOT_DA19 o

NOT_DA20 o

NOT_DA21 o

NOT_DA22 o

NOT_DA23 o

NOT_DA24 o

NOT_DA25 o

NOT_DA26 o

NOT_DA27 o

NOT_DA28 o

NOT_DA29 o

NOT_DA30 o

NOT_DA31 o

NOT_WENA o

NOT_CENA o

NOT_CONTA o

NOT_CLKA_PER o

NOT_CLKA_MINH o

NOT_CLKA_MINL

)

simulan

process_violationsA;

wakasan

laging @ (

NOT_AB0 o

NOT_AB1 o

NOT_AB2 o

NOT_AB3 o

NOT_AB4 o

NOT_AB5 o

NOT_AB6 o

NOT_AB7 o

NOT_AB8 o

NOT_AB9 o

NOT_DB0 o

NOT_DB1 o

NOT_DB2 o

NOT_DB3 o

NOT_DB4 o

NOT_DB5 o

NOT_DB6 o

NOT_DB7 o

NOT_DB8 o

NOT_DB9 o

NOT_DB10 o

NOT_DB11 o

NOT_DB12 o

NOT_DB13 o

NOT_DB14 o

NOT_DB15 o

NOT_DB16 o

NOT_DB17 o

NOT_DB18 o

NOT_DB19 o

NOT_DB20 o

NOT_DB21 o

NOT_DB22 o

NOT_DB23 o

NOT_DB24 o

NOT_DB25 o

NOT_DB26 o

NOT_DB27 o

NOT_DB28 o

NOT_DB29 o

NOT_DB30 o

NOT_DB31 o

NOT_WENB o

NOT_CENB o

NOT_CONTB o

NOT_CLKB_PER o

NOT_CLKB_MINH o

NOT_CLKB_MINL

)

simulan

process_violationsB;

wakasanlaging @ (_CLKA)

simulan

casez ((LAST_CLKA, _CLKA))

2'b01: magsimula

latch_Ainputs;

update_Alogic;

mem_cycleA;

wakasan2'b10,

2'bx?,

2'b00,

2'b11:;2'b? X: magsimula

x_mem;

read_memA (0,1);

wakasanendcase

LAST_CLKA = _CLKA;

wakasan

laging @ (_CLKB)

simulan

casez ((LAST_CLKB, _CLKB))

2'b01: magsimula

latch_Binputs;

update_Blogic;

mem_cycleB;

wakasan2'b10,

2'bx?,

2'b00,

2'b11:;2'b? X: magsimula

x_mem;

read_memB (0,1);

wakasanendcase

LAST_CLKB = _CLKB;

wakasantukuyin ang

$ setuphold (posedge CLKA, posedge CENA, 1,000, 0,500, NOT_CENA);

$ setuphold (posedge CLKA, negedge CENA, 1,000, 0,500, NOT_CENA);

$ setuphold (posedge CLKA & & & re_flagA, posedge WENA, 1,000, 0,500, NOT_WENA);

$ setuphold (posedge CLKA & & & re_flagA, negedge WENA, 1,000, 0,500, NOT_WENA);

$ setuphold (posedge CLKA & & & re_flagA, posedge Aa [0], 1,000, 0,500, NOT_AA0);

$ setuphold (posedge CLKA & & & re_flagA, negedge Aa [0], 1,000, 0,500, NOT_AA0);

$ setuphold (posedge CLKA & & & re_flagA, posedge Aa [1], 1,000, 0,500, NOT_AA1);

$ setuphold (posedge CLKA & & & re_flagA, negedge Aa [1], 1,000, 0,500, NOT_AA1);

$ setuphold (posedge CLKA & & & re_flagA, posedge Aa [2], 1,000, 0,500, NOT_AA2);

$ setuphold (posedge CLKA & & & re_flagA, negedge Aa [2], 1,000, 0,500, NOT_AA2);

$ setuphold (posedge CLKA & & & re_flagA, posedge Aa [3], 1,000, 0,500, NOT_AA3);

$ setuphold (posedge CLKA & & & re_flagA, negedge Aa [3], 1,000, 0,500, NOT_AA3);

$ setuphold (posedge CLKA & & & re_flagA, posedge Aa [4], 1,000, 0,500, NOT_AA4);

$ setuphold (posedge CLKA & & & re_flagA, negedge Aa [4], 1,000, 0,500, NOT_AA4);

$ setuphold (posedge CLKA & & & re_flagA, posedge Aa [5], 1,000, 0,500, NOT_AA5);

$ setuphold (posedge CLKA & & & re_flagA, negedge Aa [5], 1,000, 0,500, NOT_AA5);

$ setuphold (posedge CLKA & & & re_flagA, posedge Aa [6], 1,000, 0,500, NOT_AA6);

$ setuphold (posedge CLKA & & & re_flagA, negedge Aa [6], 1,000, 0,500, NOT_AA6);

$ setuphold (posedge CLKA & & & re_flagA, posedge Aa [7], 1,000, 0,500, NOT_AA7);

$ setuphold (posedge CLKA & & & re_flagA, negedge Aa [7], 1,000, 0,500, NOT_AA7);

$ setuphold (posedge CLKA & & & re_flagA, posedge Aa [8], 1,000, 0,500, NOT_AA8);

$ setuphold (posedge CLKA & & & re_flagA, negedge Aa [8], 1,000, 0,500, NOT_AA8);

$ setuphold (posedge CLKA & & & re_flagA, posedge Aa [9], 1,000, 0,500, NOT_AA9);

$ setuphold (posedge CLKA & & & re_flagA, negedge Aa [9], 1,000, 0,500, NOT_AA9);

$ setuphold (posedge CLKA & & & re_data_flagA, posedge DA [0], 1,000, 0,500, NOT_DA0);

$ setuphold (posedge CLKA & & & re_data_flagA, negedge DA [0], 1,000, 0,500, NOT_DA0);

$ setuphold (posedge CLKA & & & re_data_flagA, posedge DA [1], 1,000, 0,500, NOT_DA1);

$ setuphold (posedge CLKA & & & re_data_flagA, negedge DA [1], 1,000, 0,500, NOT_DA1);

$ setuphold (posedge CLKA & & & re_data_flagA, posedge DA [2], 1,000, 0,500, NOT_DA2);

$ setuphold (posedge CLKA & & & re_data_flagA, negedge DA [2], 1,000, 0,500, NOT_DA2);

$ setuphold (posedge CLKA & & & re_data_flagA, posedge DA [3], 1,000, 0,500, NOT_DA3);

$ setuphold (posedge CLKA & & & re_data_flagA, negedge DA [3], 1,000, 0,500, NOT_DA3);

$ setuphold (posedge CLKA & & & re_data_flagA, posedge DA [4], 1,000, 0,500, NOT_DA4);

$ setuphold (posedge CLKA & & & re_data_flagA, negedge DA [4], 1,000, 0,500, NOT_DA4);

$ setuphold (posedge CLKA & & & re_data_flagA, posedge DA [5], 1,000, 0,500, NOT_DA5);

$ setuphold (posedge CLKA & & & re_data_flagA, negedge DA [5], 1,000, 0,500, NOT_DA5);

$ setuphold (posedge CLKA & & & re_data_flagA, posedge DA [6], 1,000, 0,500, NOT_DA6);

$ setuphold (posedge CLKA & & & re_data_flagA, negedge DA [6], 1,000, 0,500, NOT_DA6);

$ setuphold (posedge CLKA & & & re_data_flagA, posedge DA [7], 1,000, 0,500, NOT_DA7);

$ setuphold (posedge CLKA & & & re_data_flagA, negedge DA [7], 1,000, 0,500, NOT_DA7);

$ setuphold (posedge CLKA & & & re_data_flagA, posedge DA [8], 1,000, 0,500, NOT_DA8);

$ setuphold (posedge CLKA & & & re_data_flagA, negedge DA [8], 1,000, 0,500, NOT_DA8);

$ setuphold (posedge CLKA & & & re_data_flagA, posedge DA [9], 1,000, 0,500, NOT_DA9);

$ setuphold (posedge CLKA & & & re_data_flagA, negedge DA [9], 1,000, 0,500, NOT_DA9);

$ setuphold (posedge CLKA & & & re_data_flagA, posedge DA [10], 1,000, 0,500, NOT_DA10);

$ setuphold (posedge CLKA & & & re_data_flagA, negedge DA [10], 1,000, 0,500, NOT_DA10);

$ setuphold (posedge CLKA & & & re_data_flagA, posedge DA [11], 1,000, 0,500, NOT_DA11);

$ setuphold (posedge CLKA & & & re_data_flagA, negedge DA [11], 1,000, 0,500, NOT_DA11);

$ setuphold (posedge CLKA & & & re_data_flagA, posedge DA [12], 1,000, 0,500, NOT_DA12);

$ setuphold (posedge CLKA & & & re_data_flagA, negedge DA [12], 1,000, 0,500, NOT_DA12);

$ setuphold (posedge CLKA & & & re_data_flagA, posedge DA [13], 1,000, 0,500, NOT_DA13);

$ setuphold (posedge CLKA & & & re_data_flagA, negedge DA [13], 1,000, 0,500, NOT_DA13);

$ setuphold (posedge CLKA & & & re_data_flagA, posedge DA [14], 1,000, 0,500, NOT_DA14);

$ setuphold (posedge CLKA & & & re_data_flagA, negedge DA [14], 1,000, 0,500, NOT_DA14);

$ setuphold (posedge CLKA & & & re_data_flagA, posedge DA [15], 1,000, 0,500, NOT_DA15);

$ setuphold (posedge CLKA & & & re_data_flagA, negedge DA [15], 1,000, 0,500, NOT_DA15);

$ setuphold (posedge CLKA & & & re_data_flagA, posedge DA [16], 1,000, 0,500, NOT_DA16);

$ setuphold (posedge CLKA & & & re_data_flagA, negedge DA [16], 1,000, 0,500, NOT_DA16);

$ setuphold (posedge CLKA & & & re_data_flagA, posedge DA [17], 1,000, 0,500, NOT_DA17);

$ setuphold (posedge CLKA & & & re_data_flagA, negedge DA [17], 1,000, 0,500, NOT_DA17);

$ setuphold (posedge CLKA & & & re_data_flagA, posedge DA [18], 1,000, 0,500, NOT_DA18);

$ setuphold (posedge CLKA & & & re_data_flagA, negedge DA [18], 1,000, 0,500, NOT_DA18);

$ setuphold (posedge CLKA & & & re_data_flagA, posedge DA [19], 1,000, 0,500, NOT_DA19);

$ setuphold (posedge CLKA & & & re_data_flagA, negedge DA [19], 1,000, 0,500, NOT_DA19);

$ setuphold (posedge CLKA & & & re_data_flagA, posedge DA [20], 1,000, 0,500, NOT_DA20);

$ setuphold (posedge CLKA & & & re_data_flagA, negedge DA [20], 1,000, 0,500, NOT_DA20);

$ setuphold (posedge CLKA & & & re_data_flagA, posedge DA [21], 1,000, 0,500, NOT_DA21);

$ setuphold (posedge CLKA & & & re_data_flagA, negedge DA [21], 1,000, 0,500, NOT_DA21);

$ setuphold (posedge CLKA & & & re_data_flagA, posedge DA [22], 1,000, 0,500, NOT_DA22);

$ setuphold (posedge CLKA & & & re_data_flagA, negedge DA [22], 1,000, 0,500, NOT_DA22);

$ setuphold (posedge CLKA & & & re_data_flagA, posedge DA [23], 1,000, 0,500, NOT_DA23);

$ setuphold (posedge CLKA & & & re_data_flagA, negedge DA [23], 1,000, 0,500, NOT_DA23);

$ setuphold (posedge CLKA & & & re_data_flagA, posedge DA [24], 1,000, 0,500, NOT_DA24);

$ setuphold (posedge CLKA & & & re_data_flagA, negedge DA [24], 1,000, 0,500, NOT_DA24);

$ setuphold (posedge CLKA & & & re_data_flagA, posedge DA [25], 1,000, 0,500, NOT_DA25);

$ setuphold (posedge CLKA & & & re_data_flagA, negedge DA [25], 1,000, 0,500, NOT_DA25);

$ setuphold (posedge CLKA & & & re_data_flagA, posedge DA [26], 1,000, 0,500, NOT_DA26);

$ setuphold (posedge CLKA & & & re_data_flagA, negedge DA [26], 1,000, 0,500, NOT_DA26);

$ setuphold (posedge CLKA & & & re_data_flagA, posedge DA [27], 1,000, 0,500, NOT_DA27);

$ setuphold (posedge CLKA & & & re_data_flagA, negedge DA [27], 1,000, 0,500, NOT_DA27);

$ setuphold (posedge CLKA & & & re_data_flagA, posedge DA [28], 1,000, 0,500, NOT_DA28);

$ setuphold (posedge CLKA & & & re_data_flagA, negedge DA [28], 1,000, 0,500, NOT_DA28);

$ setuphold (posedge CLKA & & & re_data_flagA, posedge DA [29], 1,000, 0,500, NOT_DA29);

$ setuphold (posedge CLKA & & & re_data_flagA, negedge DA [29], 1,000, 0,500, NOT_DA29);

$ setuphold (posedge CLKA & & & re_data_flagA, posedge DA [30], 1,000, 0,500, NOT_DA30);

$ setuphold (posedge CLKA & & & re_data_flagA, negedge DA [30], 1,000, 0,500, NOT_DA30);

$ setuphold (posedge CLKA & & & re_data_flagA, posedge DA [31], 1,000, 0,500, NOT_DA31);

$ setuphold (posedge CLKA & & & re_data_flagA, negedge DA [31], 1,000, 0,500, NOT_DA31);

$ setuphold (posedge CLKB, posedge CENB, 1,000, 0,500, NOT_CENB);

$ setuphold (posedge CLKB, negedge CENB, 1,000, 0,500, NOT_CENB);

$ setuphold (posedge CLKB & & & re_flagB, posedge WENB, 1,000, 0,500, NOT_WENB);

$ setuphold (posedge CLKB & & & re_flagB, negedge WENB, 1,000, 0,500, NOT_WENB);

$ setuphold (posedge CLKB & & & re_flagB, posedge AB [0], 1,000, 0,500, NOT_AB0);

$ setuphold (posedge CLKB & & & re_flagB, negedge AB [0], 1,000, 0,500, NOT_AB0);

$ setuphold (posedge CLKB & & & re_flagB, posedge AB [1], 1,000, 0,500, NOT_AB1);

$ setuphold (posedge CLKB & & & re_flagB, negedge AB [1], 1,000, 0,500, NOT_AB1);

$ setuphold (posedge CLKB & & & re_flagB, posedge AB [2], 1,000, 0,500, NOT_AB2);

$ setuphold (posedge CLKB & & & re_flagB, negedge AB [2], 1,000, 0,500, NOT_AB2);

$ setuphold (posedge CLKB & & & re_flagB, posedge AB [3], 1,000, 0,500, NOT_AB3);

$ setuphold (posedge CLKB & & & re_flagB, negedge AB [3], 1,000, 0,500, NOT_AB3);

$ setuphold (posedge CLKB & & & re_flagB, posedge AB [4], 1,000, 0,500, NOT_AB4);

$ setuphold (posedge CLKB & & & re_flagB, negedge AB [4], 1,000, 0,500, NOT_AB4);

$ setuphold (posedge CLKB & & & re_flagB, posedge AB [5], 1,000, 0,500, NOT_AB5);

$ setuphold (posedge CLKB & & & re_flagB, negedge AB [5], 1,000, 0,500, NOT_AB5);

$ setuphold (posedge CLKB & & & re_flagB, posedge AB [6], 1,000, 0,500, NOT_AB6);

$ setuphold (posedge CLKB & & & re_flagB, negedge AB [6], 1,000, 0,500, NOT_AB6);

$ setuphold (posedge CLKB & & & re_flagB, posedge AB [7], 1,000, 0,500, NOT_AB7);

$ setuphold (posedge CLKB & & & re_flagB, negedge AB [7], 1,000, 0,500, NOT_AB7);

$ setuphold (posedge CLKB & & & re_flagB, posedge AB [8], 1,000, 0,500, NOT_AB8);

$ setuphold (posedge CLKB & & & re_flagB, negedge AB [8], 1,000, 0,500, NOT_AB8);

$ setuphold (posedge CLKB & & & re_flagB, posedge AB [9], 1,000, 0,500, NOT_AB9);

$ setuphold (posedge CLKB & & & re_flagB, negedge AB [9], 1,000, 0,500, NOT_AB9);

$ setuphold (posedge CLKB & & & re_data_flagB, posedge DB [0], 1,000, 0,500, NOT_DB0);

$ setuphold (posedge CLKB & & & re_data_flagB, negedge DB [0], 1,000, 0,500, NOT_DB0);

$ setuphold (posedge CLKB & & & re_data_flagB, posedge DB [1], 1,000, 0,500, NOT_DB1);

$ setuphold (posedge CLKB & & & re_data_flagB, negedge DB [1], 1,000, 0,500, NOT_DB1);

$ setuphold (posedge CLKB & & & re_data_flagB, posedge DB [2], 1,000, 0,500, NOT_DB2);

$ setuphold (posedge CLKB & & & re_data_flagB, negedge DB [2], 1,000, 0,500, NOT_DB2);

$ setuphold (posedge CLKB & & & re_data_flagB, posedge DB [3], 1,000, 0,500, NOT_DB3);

$ setuphold (posedge CLKB & & & re_data_flagB, negedge DB [3], 1,000, 0,500, NOT_DB3);

$ setuphold (posedge CLKB & & & re_data_flagB, posedge DB [4], 1,000, 0,500, NOT_DB4);

$setuphold(posedge CLKB &&& re_data_flagB, negedge DB[4], 1.000, 0.500, NOT_DB4);
$setuphold(posedge CLKB &&& re_data_flagB, posedge DB[5], 1.000, 0.500, NOT_DB5);
$setuphold(posedge CLKB &&& re_data_flagB, negedge DB[5], 1.000, 0.500, NOT_DB5);
$setuphold(posedge CLKB &&& re_data_flagB, posedge DB[6], 1.000, 0.500, NOT_DB6);
$setuphold(posedge CLKB &&& re_data_flagB, negedge DB[6], 1.000, 0.500, NOT_DB6);
$setuphold(posedge CLKB &&& re_data_flagB, posedge DB[7], 1.000, 0.500, NOT_DB7);
$setuphold(posedge CLKB &&& re_data_flagB, negedge DB[7], 1.000, 0.500, NOT_DB7);
$setuphold(posedge CLKB &&& re_data_flagB, posedge DB[8], 1.000, 0.500, NOT_DB8);
$setuphold(posedge CLKB &&& re_data_flagB, negedge DB[8], 1.000, 0.500, NOT_DB8);
$setuphold(posedge CLKB &&& re_data_flagB, posedge DB[9], 1.000, 0.500, NOT_DB9);
$setuphold(posedge CLKB &&& re_data_flagB, negedge DB[9], 1.000, 0.500, NOT_DB9);
$setuphold(posedge CLKB &&& re_data_flagB, posedge DB[10], 1.000, 0.500, NOT_DB10);
$setuphold(posedge CLKB &&& re_data_flagB, negedge DB[10], 1.000, 0.500, NOT_DB10);
$setuphold(posedge CLKB &&& re_data_flagB, posedge DB[11], 1.000, 0.500, NOT_DB11);
$setuphold(posedge CLKB &&& re_data_flagB, negedge DB[11], 1.000, 0.500, NOT_DB11);
$setuphold(posedge CLKB &&& re_data_flagB, posedge DB[12], 1.000, 0.500, NOT_DB12);
$setuphold(posedge CLKB &&& re_data_flagB, negedge DB[12], 1.000, 0.500, NOT_DB12);
$setuphold(posedge CLKB &&& re_data_flagB, posedge DB[13], 1.000, 0.500, NOT_DB13);
$setuphold(posedge CLKB &&& re_data_flagB, negedge DB[13], 1.000, 0.500, NOT_DB13);
$setuphold(posedge CLKB &&& re_data_flagB, posedge DB[14], 1.000, 0.500, NOT_DB14);
$setuphold(posedge CLKB &&& re_data_flagB, negedge DB[14], 1.000, 0.500, NOT_DB14);
$setuphold(posedge CLKB &&& re_data_flagB, posedge DB[15], 1.000, 0.500, NOT_DB15);
$setuphold(posedge CLKB &&& re_data_flagB, negedge DB[15], 1.000, 0.500, NOT_DB15);
$setuphold(posedge CLKB &&& re_data_flagB, posedge DB[16], 1.000, 0.500, NOT_DB16);
$setuphold(posedge CLKB &&& re_data_flagB, negedge DB[16], 1.000, 0.500, NOT_DB16);
$setuphold(posedge CLKB &&& re_data_flagB, posedge DB[17], 1.000, 0.500, NOT_DB17);
$setuphold(posedge CLKB &&& re_data_flagB, negedge DB[17], 1.000, 0.500, NOT_DB17);
$setuphold(posedge CLKB &&& re_data_flagB, posedge DB[18], 1.000, 0.500, NOT_DB18);
$setuphold(posedge CLKB &&& re_data_flagB, negedge DB[18], 1.000, 0.500, NOT_DB18);
$setuphold(posedge CLKB &&& re_data_flagB, posedge DB[19], 1.000, 0.500, NOT_DB19);
$setuphold(posedge CLKB &&& re_data_flagB, negedge DB[19], 1.000, 0.500, NOT_DB19);
$setuphold(posedge CLKB &&& re_data_flagB, posedge DB[20], 1.000, 0.500, NOT_DB20);
$setuphold(posedge CLKB &&& re_data_flagB, negedge DB[20], 1.000, 0.500, NOT_DB20);
$setuphold(posedge CLKB &&& re_data_flagB, posedge DB[21], 1.000, 0.500, NOT_DB21);
$setuphold(posedge CLKB &&& re_data_flagB, negedge DB[21], 1.000, 0.500, NOT_DB21);
$setuphold(posedge CLKB &&& re_data_flagB, posedge DB[22], 1.000, 0.500, NOT_DB22);
$setuphold(posedge CLKB &&& re_data_flagB, negedge DB[22], 1.000, 0.500, NOT_DB22);
$setuphold(posedge CLKB &&& re_data_flagB, posedge DB[23], 1.000, 0.500, NOT_DB23);
$setuphold(posedge CLKB &&& re_data_flagB, negedge DB[23], 1.000, 0.500, NOT_DB23);
$setuphold(posedge CLKB &&& re_data_flagB, posedge DB[24], 1.000, 0.500, NOT_DB24);
$setuphold(posedge CLKB &&& re_data_flagB, negedge DB[24], 1.000, 0.500, NOT_DB24);
$setuphold(posedge CLKB &&& re_data_flagB, posedge DB[25], 1.000, 0.500, NOT_DB25);
$setuphold(posedge CLKB &&& re_data_flagB, negedge DB[25], 1.000, 0.500, NOT_DB25);
$setuphold(posedge CLKB &&& re_data_flagB, posedge DB[26], 1.000, 0.500, NOT_DB26);
$setuphold(posedge CLKB &&& re_data_flagB, negedge DB[26], 1.000, 0.500, NOT_DB26);
$setuphold(posedge CLKB &&& re_data_flagB, posedge DB[27], 1.000, 0.500, NOT_DB27);
$setuphold(posedge CLKB &&& re_data_flagB, negedge DB[27], 1.000, 0.500, NOT_DB27);
$setuphold(posedge CLKB &&& re_data_flagB, posedge DB[28], 1.000, 0.500, NOT_DB28);
$setuphold(posedge CLKB &&& re_data_flagB, negedge DB[28], 1.000, 0.500, NOT_DB28);
$setuphold(posedge CLKB &&& re_data_flagB, posedge DB[29], 1.000, 0.500, NOT_DB29);
$setuphold(posedge CLKB &&& re_data_flagB, negedge DB[29], 1.000, 0.500, NOT_DB29);
$setuphold(posedge CLKB &&& re_data_flagB, posedge DB[30], 1.000, 0.500, NOT_DB30);
$setuphold(posedge CLKB &&& re_data_flagB, negedge DB[30], 1.000, 0.500, NOT_DB30);
$setuphold(posedge CLKB &&& re_data_flagB, posedge DB[31], 1.000, 0.500, NOT_DB31);
$setuphold(posedge CLKB &&& re_data_flagB, negedge DB[31], 1.000, 0.500, NOT_DB31);
$setup(posedge CLKA, posedge CLKB &&& contB_flag, 3.000, NOT_CONTB);
$setup(posedge CLKB, posedge CLKA &&& contA_flag, 3.000, NOT_CONTA);
$hold(posedge CLKA, posedge CLKB &&& cont_flag, 0.001, NOT_CONTB);

$period(posedge CLKA, 3.000, NOT_CLKA_PER);
$width(posedge CLKA, 1.000, 0, NOT_CLKA_MINH);
$width(negedge CLKA, 1.000, 0, NOT_CLKA_MINL);
$period(posedge CLKB, 3.000, NOT_CLKB_PER);
$width(posedge CLKB, 1.000, 0, NOT_CLKB_MINH);
$width(negedge CLKB, 1.000, 0, NOT_CLKB_MINL);

(CLKA => QA[0])=(1.000, 1.000, 0.500, 1.000, 0.500, 1.000);
(CLKA => QA[1])=(1.000, 1.000, 0.500, 1.000, 0.500, 1.000);
(CLKA => QA[2])=(1.000, 1.000, 0.500, 1.000, 0.500, 1.000);
(CLKA => QA[3])=(1.000, 1.000, 0.500, 1.000, 0.500, 1.000);
(CLKA => QA[4])=(1.000, 1.000, 0.500, 1.000, 0.500, 1.000);
(CLKA => QA[5])=(1.000, 1.000, 0.500, 1.000, 0.500, 1.000);
(CLKA => QA[6])=(1.000, 1.000, 0.500, 1.000, 0.500, 1.000);
(CLKA => QA[7])=(1.000, 1.000, 0.500, 1.000, 0.500, 1.000);
(CLKA => QA[8])=(1.000, 1.000, 0.500, 1.000, 0.500, 1.000);
(CLKA => QA[9])=(1.000, 1.000, 0.500, 1.000, 0.500, 1.000);
(CLKA => QA[10])=(1.000, 1.000, 0.500, 1.000, 0.500, 1.000);
(CLKA => QA[11])=(1.000, 1.000, 0.500, 1.000, 0.500, 1.000);
(CLKA => QA[12])=(1.000, 1.000, 0.500, 1.000, 0.500, 1.000);
(CLKA => QA[13])=(1.000, 1.000, 0.500, 1.000, 0.500, 1.000);
(CLKA => QA[14])=(1.000, 1.000, 0.500, 1.000, 0.500, 1.000);
(CLKA => QA[15])=(1.000, 1.000, 0.500, 1.000, 0.500, 1.000);
(CLKA => QA[16])=(1.000, 1.000, 0.500, 1.000, 0.500, 1.000);
(CLKA => QA[17])=(1.000, 1.000, 0.500, 1.000, 0.500, 1.000);
(CLKA => QA[18])=(1.000, 1.000, 0.500, 1.000, 0.500, 1.000);
(CLKA => QA[19])=(1.000, 1.000, 0.500, 1.000, 0.500, 1.000);
(CLKA => QA[20])=(1.000, 1.000, 0.500, 1.000, 0.500, 1.000);
(CLKA => QA[21])=(1.000, 1.000, 0.500, 1.000, 0.500, 1.000);
(CLKA => QA[22])=(1.000, 1.000, 0.500, 1.000, 0.500, 1.000);
(CLKA => QA[23])=(1.000, 1.000, 0.500, 1.000, 0.500, 1.000);
(CLKA => QA[24])=(1.000, 1.000, 0.500, 1.000, 0.500, 1.000);
(CLKA => QA[25])=(1.000, 1.000, 0.500, 1.000, 0.500, 1.000);
(CLKA => QA[26])=(1.000, 1.000, 0.500, 1.000, 0.500, 1.000);
(CLKA => QA[27])=(1.000, 1.000, 0.500, 1.000, 0.500, 1.000);
(CLKA => QA[28])=(1.000, 1.000, 0.500, 1.000, 0.500, 1.000);
(CLKA => QA[29])=(1.000, 1.000, 0.500, 1.000, 0.500, 1.000);
(CLKA => QA[30])=(1.000, 1.000, 0.500, 1.000, 0.500, 1.000);
(CLKA => QA[31])=(1.000, 1.000, 0.500, 1.000, 0.500, 1.000);
(OENA => QA[0])=(1.000, 1.000, 1.000, 1.000, 1.000, 1.000);
(OENA => QA[1])=(1.000, 1.000, 1.000, 1.000, 1.000, 1.000);
(OENA => QA[2])=(1.000, 1.000, 1.000, 1.000, 1.000, 1.000);
(OENA => QA[3])=(1.000, 1.000, 1.000, 1.000, 1.000, 1.000);
(OENA => QA[4])=(1.000, 1.000, 1.000, 1.000, 1.000, 1.000);
(OENA => QA[5])=(1.000, 1.000, 1.000, 1.000, 1.000, 1.000);
(OENA => QA[6])=(1.000, 1.000, 1.000, 1.000, 1.000, 1.000);
(OENA => QA[7])=(1.000, 1.000, 1.000, 1.000, 1.000, 1.000);
(OENA => QA[8])=(1.000, 1.000, 1.000, 1.000, 1.000, 1.000);
(OENA => QA[9])=(1.000, 1.000, 1.000, 1.000, 1.000, 1.000);
(OENA => QA[10])=(1.000, 1.000, 1.000, 1.000, 1.000, 1.000);
(OENA => QA[11])=(1.000, 1.000, 1.000, 1.000, 1.000, 1.000);
(OENA => QA[12])=(1.000, 1.000, 1.000, 1.000, 1.000, 1.000);
(OENA => QA[13])=(1.000, 1.000, 1.000, 1.000, 1.000, 1.000);
(OENA => QA[14])=(1.000, 1.000, 1.000, 1.000, 1.000, 1.000);
(OENA => QA[15])=(1.000, 1.000, 1.000, 1.000, 1.000, 1.000);
(OENA => QA[16])=(1.000, 1.000, 1.000, 1.000, 1.000, 1.000);
(OENA => QA[17])=(1.000, 1.000, 1.000, 1.000, 1.000, 1.000);
(OENA => QA[18])=(1.000, 1.000, 1.000, 1.000, 1.000, 1.000);
(OENA => QA[19])=(1.000, 1.000, 1.000, 1.000, 1.000, 1.000);
(OENA => QA[20])=(1.000, 1.000, 1.000, 1.000, 1.000, 1.000);
(OENA => QA[21])=(1.000, 1.000, 1.000, 1.000, 1.000, 1.000);
(OENA => QA[22])=(1.000, 1.000, 1.000, 1.000, 1.000, 1.000);
(OENA => QA[23])=(1.000, 1.000, 1.000, 1.000, 1.000, 1.000);
(OENA => QA[24])=(1.000, 1.000, 1.000, 1.000, 1.000, 1.000);
(OENA => QA[25])=(1.000, 1.000, 1.000, 1.000, 1.000, 1.000);
(OENA => QA[26])=(1.000, 1.000, 1.000, 1.000, 1.000, 1.000);
(OENA => QA[27])=(1.000, 1.000, 1.000, 1.000, 1.000, 1.000);
(OENA => QA[28])=(1.000, 1.000, 1.000, 1.000, 1.000, 1.000);
(OENA => QA[29])=(1.000, 1.000, 1.000, 1.000, 1.000, 1.000);
(OENA => QA[30])=(1.000, 1.000, 1.000, 1.000, 1.000, 1.000);
(OENA => QA[31])=(1.000, 1.000, 1.000, 1.000, 1.000, 1.000);
(CLKB => QB[0])=(1.000, 1.000, 0.500, 1.000, 0.500, 1.000);
(CLKB => QB[1])=(1.000, 1.000, 0.500, 1.000, 0.500, 1.000);
(CLKB => QB[2])=(1.000, 1.000, 0.500, 1.000, 0.500, 1.000);
(CLKB => QB[3])=(1.000, 1.000, 0.500, 1.000, 0.500, 1.000);
(CLKB => QB[4])=(1.000, 1.000, 0.500, 1.000, 0.500, 1.000);
(CLKB => QB[5])=(1.000, 1.000, 0.500, 1.000, 0.500, 1.000);
(CLKB => QB[6])=(1.000, 1.000, 0.500, 1.000, 0.500, 1.000);
(CLKB => QB[7])=(1.000, 1.000, 0.500, 1.000, 0.500, 1.000);
(CLKB => QB[8])=(1.000, 1.000, 0.500, 1.000, 0.500, 1.000);
(CLKB => QB[9])=(1.000, 1.000, 0.500, 1.000, 0.500, 1.000);
(CLKB => QB[10])=(1.000, 1.000, 0.500, 1.000, 0.500, 1.000);
(CLKB => QB[11])=(1.000, 1.000, 0.500, 1.000, 0.500, 1.000);
(CLKB => QB[12])=(1.000, 1.000, 0.500, 1.000, 0.500, 1.000);
(CLKB => QB[13])=(1.000, 1.000, 0.500, 1.000, 0.500, 1.000);
(CLKB => QB[14])=(1.000, 1.000, 0.500, 1.000, 0.500, 1.000);
(CLKB => QB[15])=(1.000, 1.000, 0.500, 1.000, 0.500, 1.000);
(CLKB => QB[16])=(1.000, 1.000, 0.500, 1.000, 0.500, 1.000);
(CLKB => QB[17])=(1.000, 1.000, 0.500, 1.000, 0.500, 1.000);
(CLKB => QB[18])=(1.000, 1.000, 0.500, 1.000, 0.500, 1.000);
(CLKB => QB[19])=(1.000, 1.000, 0.500, 1.000, 0.500, 1.000);
(CLKB => QB[20])=(1.000, 1.000, 0.500, 1.000, 0.500, 1.000);
(CLKB => QB[21])=(1.000, 1.000, 0.500, 1.000, 0.500, 1.000);
(CLKB => QB[22])=(1.000, 1.000, 0.500, 1.000, 0.500, 1.000);
(CLKB => QB[23])=(1.000, 1.000, 0.500, 1.000, 0.500, 1.000);
(CLKB => QB[24])=(1.000, 1.000, 0.500, 1.000, 0.500, 1.000);
(CLKB => QB[25])=(1.000, 1.000, 0.500, 1.000, 0.500, 1.000);
(CLKB => QB[26])=(1.000, 1.000, 0.500, 1.000, 0.500, 1.000);
(CLKB => QB[27])=(1.000, 1.000, 0.500, 1.000, 0.500, 1.000);
(CLKB => QB[28])=(1.000, 1.000, 0.500, 1.000, 0.500, 1.000);
(CLKB => QB[29])=(1.000, 1.000, 0.500, 1.000, 0.500, 1.000);
(CLKB => QB[30])=(1.000, 1.000, 0.500, 1.000, 0.500, 1.000);
(CLKB => QB[31])=(1.000, 1.000, 0.500, 1.000, 0.500, 1.000);
(OENB => QB[0])=(1.000, 1.000, 1.000, 1.000, 1.000, 1.000);
(OENB => QB[1])=(1.000, 1.000, 1.000, 1.000, 1.000, 1.000);
(OENB => QB[2])=(1.000, 1.000, 1.000, 1.000, 1.000, 1.000);
(OENB => QB[3])=(1.000, 1.000, 1.000, 1.000, 1.000, 1.000);
(OENB => QB[4])=(1.000, 1.000, 1.000, 1.000, 1.000, 1.000);
(OENB => QB[5])=(1.000, 1.000, 1.000, 1.000, 1.000, 1.000);
(OENB => QB[6])=(1.000, 1.000, 1.000, 1.000, 1.000, 1.000);
(OENB => QB[7])=(1.000, 1.000, 1.000, 1.000, 1.000, 1.000);
(OENB => QB[8])=(1.000, 1.000, 1.000, 1.000, 1.000, 1.000);
(OENB => QB[9])=(1.000, 1.000, 1.000, 1.000, 1.000, 1.000);
(OENB => QB[10])=(1.000, 1.000, 1.000, 1.000, 1.000, 1.000);
(OENB => QB[11])=(1.000, 1.000, 1.000, 1.000, 1.000, 1.000);
(OENB => QB[12])=(1.000, 1.000, 1.000, 1.000, 1.000, 1.000);
(OENB => QB[13])=(1.000, 1.000, 1.000, 1.000, 1.000, 1.000);
(OENB => QB[14])=(1.000, 1.000, 1.000, 1.000, 1.000, 1.000);
(OENB => QB[15])=(1.000, 1.000, 1.000, 1.000, 1.000, 1.000);
(OENB => QB[16])=(1.000, 1.000, 1.000, 1.000, 1.000, 1.000);
(OENB => QB[17])=(1.000, 1.000, 1.000, 1.000, 1.000, 1.000);
(OENB => QB[18])=(1.000, 1.000, 1.000, 1.000, 1.000, 1.000);
(OENB => QB[19])=(1.000, 1.000, 1.000, 1.000, 1.000, 1.000);
(OENB => QB[20])=(1.000, 1.000, 1.000, 1.000, 1.000, 1.000);
(OENB => QB[21])=(1.000, 1.000, 1.000, 1.000, 1.000, 1.000);
(OENB => QB[22])=(1.000, 1.000, 1.000, 1.000, 1.000, 1.000);
(OENB => QB[23])=(1.000, 1.000, 1.000, 1.000, 1.000, 1.000);
(OENB => QB[24])=(1.000, 1.000, 1.000, 1.000, 1.000, 1.000);
(OENB => QB[25])=(1.000, 1.000, 1.000, 1.000, 1.000, 1.000);
(OENB => QB[26])=(1.000, 1.000, 1.000, 1.000, 1.000, 1.000);
(OENB => QB[27])=(1.000, 1.000, 1.000, 1.000, 1.000, 1.000);
(OENB => QB[28])=(1.000, 1.000, 1.000, 1.000, 1.000, 1.000);
(OENB => QB[29])=(1.000, 1.000, 1.000, 1.000, 1.000, 1.000);
(OENB => QB[30])=(1.000, 1.000, 1.000, 1.000, 1.000, 1.000);
(OENB => QB[31])=(1.000, 1.000, 1.000, 1.000, 1.000, 1.000);
endspecify

endmodule
`endcelldefine
 
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